View CXD1945R_7677155.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the CXD1945R is a physical layer ic conforming to ieee 1394-1995 that supports transfer speeds of 200/100mbit/s. this chip has three ports for 1394 cable interface, an interface to a link layer ic, received packet data regeneration repeat, and arbitration/bus initialization logic. the CXD1945R supports ieee 1394 protocol physical layer functions. features low voltage amplitude differential transceiver conforming to ieee 1394-1995 supports 196.603mbit/s and 98.304mbit/s data rates active line detection function for when a port is connected to an active node automatic shutdown function for inactive ports to save power bus initialization and arbitration state machine logic resynchronization of received data to local clock link-on packet recognition ds link encoding/decoding built-in 196.603mhz pll cable power status detects drops in the power supply from the cable link power status detects the link layer ic power status supports configuration manager capable and power class definition pins 3-port independent tpbias applications digital camera, digital vcr, digital audio, electronic musical instruments, scanner, printer, various storage devices absolute maximum ratings supply voltage v dd ?.5 to +5.0 v input voltage v in ?.5 to v dd + 0.5 v output voltage v out ?.5 to v dd + 0.5 v storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd 3.0 to 3.6 v input voltage v in 0 to v dd v output voltage v out 0 to v dd v ambient temperature t a 0 to +70 ? ieee 1394 3-port 100/200mbps cable transceiver/arbiter ?1 e98643-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD1945R 80 pin lqfp (plastic)
? 2 CXD1945R block diagram c o n t r o l u n i t l i n k i n t e r f a c e d s - l i n k e n c o d e r / d e c o d e r t p b i a s g e n . c a b l e p o w e r s t a t u s v o l t a g e - c u r r e n t g e n . t r a n s m i t t e r & r e c e i v e r t r a n s m i t t e r & r e c e i v e r t r a n s m i t t e r & r e c e i v e r 2 4 . 5 7 6 m h z c r y s t a l o s c i l l a t o r p l l l p s d i r e c t s c l k l r e q c t l [ 0 : 1 ] d [ 0 : 3 ] p c 0 p c 1 p c 2 c m c / l i n k o n p u r b ( p o w e r u p r e s e t ) 1 9 6 . 6 0 3 m h z c l k l o o p f i l t e r x o x i c p s t p b i a s 0 t p b i a s 1 t p b i a s 2 r e x t v r e f t p a 0 t p b 0 t p a 1 t p b 1 t p a 2 t p b 2
? 3 CXD1945R pin configuration 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 p c 1 p c 2 d v s s d v s s l p s l r e q d v d d s c l k d v s s c t l 0 c t l 1 d v d d d 0 d 1 d v s s d 2 d 3 d v d d d v s s d v s s a v s s v c o r l f a v d d 1 a v s s a v s s a v s s x i x o a v d d 1 a v s s a v d d 1 p u r b d v s s d v d d d v d d d v s s d v s s d v s s d v s s n c n c d v d d n c n c d v s s d v s s d v s s d v s s d v s s d v s s a v s s a v d d 2 d v s s t e s t 1 t e s t 0 d i r e c t c m c / l i n k o n p c 0 d v d d t p a 0 p t p a 0 n t p b 0 p t p b 0 n t p a 1 p t p a 1 n t p b 1 p t p b 1 n t p a 2 p t p a 2 n t p b 2 p t p b 2 n t p b i a s 0 t p b i a s 1 t p b i a s 2 a v d d 1 a v s s c p s r e x t v r e f
? 4 CXD1945R pin description pin no. 79, 1, 2 pc[0:2] i power class [0:2] the power_class field of the self-id packet reflects the status of this pin during the self-id period. connect to dv ss or dv dd depending on the setting. 3, 4, 9, 15, 19 to 24, 27, 66 to 71, 74 dv ss digital ground. 5 lps i link power status. monitors the link power on/off status. link power off is detected if this pin is low for 2.56 s. link power on is detected if this pin is high for 80ns. (see 3-1-2.) 6 lreq i link request. the link reads/writes the phy register and performs bus requests via this pin. (see 3-1-3.) 7, 12, 18, 25, 26, 63, 80 dv dd digital power supply. 8 sclk o 49.152mhz link system clock. the phy-link interface and cable interface are synchronized to sclk. symbol i/o description 10, 11 ctl[0:1] i/o phy-link interface control signal. (see 3-1-3.) 13, 14, 16, 17 d[0:3] i/o phy-link interface data signal. (see 3-1-3.) 29, 31, 37, 45 av dd 1 analog power supply 1. power supply for all blocks other than the cable interface driver. 30, 34 to 36, 40, 44, 72 av ss analog ground. 32, 33 xo, xi i/o crystal connection. crystal oscillator connection. the oscillator output frequency must be 24.576mhz 100ppm. use a crystal with an accuracy of 50ppm when a 10pf load is connected. (see 3-3.) 38 lf o 39 vocr i external loop filter connection. 41 vref i external reference resistor connection. connect to av ss via 18k + 510 ( 1%) external resistors and 0.01 f. 42 rext i external reference resistor connection. connect to av ss via 11k + 620 ( 1%) external resistors. 28 purb i external capacitor connection for power up reset. connect to dv ss via 0.1 f. the reset period is a minimum 15ms. the internal reset state machines are all initialized during the reset period. (see 3-4.)
? 5 CXD1945R 43 cps i cable power status detection. connect to cable power (vp) via 220k ( 5%). when not used, connect to av dd 1. (see 3-2-3.) pin no. 48 to 46 tpbias[0:2] o cable bias output. connect to av ss via 0.33 f. 57, 53, 49 tpb[0:2]n i/o arbitration/speed signal/data output. arbitration/strobe input. reverse phase i/o. 58, 54, 50 tpb[0:2]p i/o arbitration/speed signal/data output. arbitration/strobe input. forward phase i/o. 59, 55, 51 tpa[0:2]n i/o arbitration/strobe output. arbitration/speed signal/data input. reverse phase i/o. 60, 56, 52 tpa[0:2]p i/o arbitration/strobe output. arbitration/speed signal/data input. forward phase i/o. 61, 62, 64, 65 nc no connected. leave open or connect to ground (dv ss ). 73 av dd 2 analog power supply 2. power supply for cable interface driver. 76, 75 test[0:1] i test mode control. connect to dv dd . 77 direct i phy-link interface operating mode setting. connect to dv dd . the CXD1945R supports only dc connection. 78 cmc/ linkon i/o configuration manager capable setting/link-on signal output. the contender field of the self-id packet reflects the status of this pin during the self-id period, and then this pin functions as the link-on output after that. link-on is a 6.144mhz, duty 50% ac signal. (see 3-1-4.) symbol i/o description
? 6 CXD1945R electrical characteristics 1. dc characteristics electrical characteristics under the recommended operating conditions (unless otherwise specified) link interface symbol v t+ item input schmitt rise threshold value pin lreq, ctl[0:1], d[0:3] conditions min. v dd /2 + 0.2 typ. max. v dd /2 + 1.0 unit v v t input schmitt fall threshold value lreq, ctl[0:1], d[0:3] v dd /2 ?1.0 v dd /2 ?0.2 v v ih high level input voltage lps, test[0:1], direct, pc[0:2], cmc/linkon v dd ?1.0 v lreq, ctl[0:1], d[0:3] v ih = v dd ?0 i ih high level input current lps, test[0:1], direct, pc[0:2], cmc/linkon v ih = v dd ?0 a v il low level input voltage lps, test[0:1], direct, pc[0:2], cmc/linkon 1.0 v lreq, ctl[0:1], d[0:3] v il = v ss 10.0 i il low level input current lps, test[0:1], direct, pc[0:2], cmc/linkon v il = v ss 10.0 a sclk, ctl[0:1], d[0:3] i oh = ?0ma v dd ?0.5 v oh high level output voltage cmc/linkon i oh = ?ma v dd ?0.5 v sclk, ctl[0:1], d[0:3] i ol = 10ma 0.5 v ol low level output voltage cmc/linkon i ol = 6ma 0.5 v i dd dynamic current consumption v dd = 3.3v 128.0 ma (v ss = 0v)
? 7 CXD1945R symbol v od v tpbias i cm z diffz item differential output amplitude tpbias output voltage tp common mode current differential input impedance conditions load 55 source 3ma, sync 1.3ma driver disabled (z state) drivers other than the speed signal enabled driver disabled (z state) min. 175 typ. max. 265 unit mv i spd tpb200mbit speed signal 2.76 4.6 ma c cm common mode input capacitance tp pins shorted z state drivers 27.6 pf 1.72 1.92 5 v ?5 ?.18 21.0 0.18 a ma k 6.9 pf v t n o c onn inactive line threshold voltage tpb common mode voltage 0.64 0.96 v v t c pwd cps threshold voltage vp pins (r = 220k ) 6.0 7.6 v z diffen differential input impedance driver enabled 3.4 k 6.9 pf cable interface
? 8 CXD1945R 2. ac characteristics link interface symbol t su t h t d t sclk t sclkh t sclkl t linkon item d, ctl and lreq setup time d, ctl and lreq hold time d and ctl output timing time sclk cycle time sclk high level time sclk low level time link-on cycle time 5 1 0 20 8 8 160 7 12 12 ns ns ns ns ns ns ns min. dc connection typ. max. unit symbol t tjitter t tskew t trf item tpa and tpb transfer jitter skew between tpa strobe and tpb data transfer tpa and tpb transfer rise and fall from 10% to 90%, via 55 and 10pf 0.25 0.15 2.2 ns ns ns conditions min. max. unit twisted pair interface s c l k t s c l k h t s c l k l t s c l k t l i n k o n l i n k - o n link interface ac characteristics (sclk, link-on)
? 9 CXD1945R s c l k t d t d t d t d c t l [ 1 : 0 ] r e c e i v e t d t d d [ 3 : 0 ] t s u t s u t h c t l [ 1 : 0 ] t r a n s m i t t h d [ 3 : 0 ] link interface ac characteristics (ctl, d) s c l k l r e q t s u t h link interface ac characteristics (lreq)
? 10 CXD1945R [1] control register 1-1. register access method normally the CXD1945R registers are accessed from the link layer ic. see "3-1-3-1. lreq" for the detailed access method. 1-2. register contents 1-2-1. register0 address 00h bits 7 to 2: physical id: physical node id (r ?initial value: 00h) indicates the id of this node determined during the self-id period. these bits are initialized by a bus reset and determined when the self-id packet is transmitted during the self-id period. the register address "00h" including these bits is automatically output to the link interface as the status transmission after transmitting the self-id packet. bit 1: r: root indicator (r ?initial value: 0h) indicates that this node is the root when "1". this bit is initialized by a bus reset and determined during the tree-id period. bit 0: cps: cable power status (r ?initial value: cps pin setting) reflects the cps pin value to indicate the cable power status. indicates that power is supplied from the cable when "1". 1-2-2. register1 address 01h bit 7: rhb: root hold bit (r/w ?initial value: 0h) requests that this node become the root at the next bus reset when "1". this bit is also automatically set by phy configuration packet transmit/receive. bit 6: ibr: indicates bus reset (r/w ?initial value: 0h) bus reset is initiated immediately when set to "1". this bit is initialized by a bus reset. bits 5 to 0: gc: gap count (r/w ?initial value: 3fh) this is the gap count value. these bits are also automatically set by phy configuration packet transmit/receive. after these bits are set, the value is held by the first bus reset, but initialized by the next bus reset. rhb gc bit7 adr. 01h bit6 ibr bit5 bit4 bit3 bit2 bit1 bit0 physical id cps bit7 adr. 00h bit6 r bit5 bit4 bit3 bit2 bit1 bit0
? 11 CXD1945R 1-2-3. register2 address 02h bits 7 to 6: spd: speed (r ?initial value: 01b) indicates the maximum transfer speed supported by the CXD1945R. "01b" is read. bits 5 to 4: reserved (r ?initial value: 0h) normally "0" (00b) is read. bits 3 to 0: np: number of ports (r ?initial value: 3h) indicates the number of ports possessed by the CXD1945R. normally "3" (0011b) is read. 1-2-4. register3 address 03h bits 7 to 6: astat0: status of tpa0 (r ?initial value: 0h) indicates the tpa0 status. the meanings of the values are as follows. 11b: z 01b: 1 10b: 0 00b: invalid bits 5 to 4: bstat0: status of tpb0 (r ?initial value: 0h) indicates the tpb0 status. the meanings of the values are as follows. 11b: z 01b: 1 10b: 0 00b: invalid bit 3: ch0: child (r ?initial value: 0h) indicates that port 0 is a child when "1", or a parent when "0". this bit is initialized by a bus reset and determined during the tree-id period. bit 2: con0: connected (r ?initial value: 0h) indicates that port 0 is connected to an opposing node when "1". the CXD1945R has a built-in connection debounce circuit, so bus reset is initiated after waiting for the 341ms period from the time cable connection is detected until the connection stabilizes. bus reset is initiated immediately when cable disconnection is detected. this bit is determined during the bus reset period. bits 1 to 0: reserved (r ?initial value: 0h) reserved. ch0 con0 astat0 reserved bstat0 bit7 adr. 03h bit6 bit5 bit4 bit3 bit2 bit1 bit0 np spd reserved bit7 adr. 02h bit6 bit5 bit4 bit3 bit2 bit1 bit0
? 12 CXD1945R ch2 con2 astat2 reserved bstat2 1-2-5. register4 address 04h bits 7 to 6: astat1: status of tpa1 (r ?initial value: 0h) indicates the tpa1 status. the meanings of the values are as follows. 11b: z 01b: 1 10b: 0 00b: invalid bits 5 to 4: bstat1: status of tpb1 (r ?initial value: 0h) indicates the tpb1 status. the meanings of the values are as follows. 11b: z 01b: 1 10b: 0 00b: invalid bit 3: ch1: child (r ?initial value: 0h) indicates that port 1 is a child when "1", or a parent when "0". this bit is initialized by a bus reset and determined during the tree-id period. bit 2: con1: connected (r ?initial value: 0h) indicates that port 1 is connected to an opposing node when "1". the CXD1945R has a built-in connection debounce circuit, so bus reset is initiated after waiting for the 341ms period from the time cable connection is detected until the connection stabilizes. bus reset is initiated immediately when cable disconnection is detected. this bit is determined during the bus reset period. bits 1 to 0: reserved (r ?initial value: 0h) reserved. 1-2-6. register5 address 05h bits 7 to 6: astat2: status of tpa2 (r ?initial value: 0h) indicates the tpa2 status. the meanings of the values are as follows. 11b: z 01b: 1 10b: 0 00b: invalid bits 5 to 4: bstat2: status of tpb2 (r ?initial value: 0h) indicates the tpb2 status. the meanings of the values are as follows. 11b: z 01b: 1 10b: 0 00b: invalid bit7 adr. 05h bit6 bit5 bit4 bit3 bit2 bit1 bit0 ch1 con1 astat1 reserved bstat1 bit7 adr. 04h bit6 bit5 bit4 bit3 bit2 bit1 bit0
? 13 CXD1945R bit 3: ch2: child (r ?initial value: 0h) indicates that port 2 is a child when "1", or a parent when "0". this bit is initialized by a bus reset and determined during the tree-id period. bit 2: con2: connected (r ?initial value: 0h) indicates that port 2 is connected to an opposing node when "1". the CXD1945R has a built-in connection debounce circuit, so bus reset is initiated after waiting for the 341ms period from the time cable connection is detected until the connection stabilizes. bus reset is initiated immediately when cable disconnection is detected. this bit is determined during the bus reset period. bits 1 to 0: reserved (r ?initial value: 0h) reserved. 1-2-7. register6 address 06h bit 7: loopint: loop interrupt (r/w ?initial value: 0h) indicates that the bus forms a loop when "1". this bit is cleared by a hardware reset or by writing "0". bit 6: cpstatint: cable power status interrupt (r/w ?initial value: 0h) indicates that the power supplied from the cable has dropped when "1". this bit is cleared by a hardware reset or by writing "0". bit 5: cpstat: cable power status (r/w ?initial value: cps pin setting) reflects the cps pin value to indicate the cable power status. indicates that power is supplied from the cable when "1". this bit has the same contents as the cps bit (address "00h" bit 0). bit 4: ididit: indicates bus reset initiated (r/w ?initial value: 0h) indicates that this node initiated the previous bus reset when "1". this bit is the same as the i (initiated_reset) field of the self-id packet. this bit is determined during bus reset. bits 3 to 0: reserved (r ?initial value: 0h) normally "0000b" is read. 1-2-8. register7 address 07h ididit bit7 adr. 06h bit6 cpstatint loopint bit5 bit4 bit3 reserved bit2 bit1 bit0 cpstat bit7 adr. 07h bit6 bit5 bit4 bit3 reserved bit2 bit1 bit0 bits 7 to 0: reserved (r ?initial value: 0h) reserved.
? 14 CXD1945R address 7 6 5 4 3 2 1 0 00h physical id r cps 01h rhb ibr gc 02h 03h 04h 05h 06h 07h 08h 09h spd astat0 astat1 astat2 reserved np bstat0 bstat1 bstat2 ch0 ch1 ch2 con0 con1 con2 reserved reserved reserved loopint cpstatint cpstat ididit reserved reserved reserved reserved isbr table 1-1. list of registers 1-2-9. register8 address 08h bit7 adr. 08h bit6 bit5 bit4 bit3 reserved bit2 bit1 bit0 bit7 adr. 09h bit6 bit5 bit4 bit3 reserved bit2 bit1 bit0 isbr bits 7 to 0: reserved (r ?initial value: 0h) reserved. 1-2-10. register9 address 09h bits 7 to 1: reserved (r ?initial value: 0h) reserved. bit0: isbr: initiate short (arbitrated) bus reset (r/w ?initial value: 0h) an arbitration short bus reset is initiated when this bit is set to "1". this bit is initialized by a bus reset. 1-3. list of registers
? 15 CXD1945R [2] data format 2-1. self-id packet the self-id packet output by the CXD1945R is comprised of 2 quadlets, and follows the format shown in fig. 2-1. fig. 2-1. self-id packet format phy_id: physical_id field this is the physical_id of the CXD1945R. l: link_active field reflects the lps pin status during self-id packet transmit. gap_cnt: gap_count field reflects the phy register1 gc value. sp: phy_speed field 00 = 98.304mbps 01 = 98.304 and 196.608mbps 10 = 98.304, 196.608 and 393.216mbps 11 = reserved available speeds are saved. fixed to "01" for the CXD1945R. del: phy_delay field 00 = 144ns or less (to 14/base_rate) 01 to 11 = reserved the repeater worst case delay time is saved. fixed to "00" for the CXD1945R. c: contender field. cmc/linkon pin setting. reflects the cmc/linkon pin setting. pwr: power_class field reflects the pc[2:0] pin setting. defined as follows for ieee 1394-1995. 000 = the node does not require power supply. 001 = the node has its own power supply and can feed a minimum of 15w. 010 = the node has its own power supply and can feed a minimum of 30w. 011 = the node has its own power supply and can feed a minimum of 45w. 100 = the node consumes a maximum of 1w of power from the cable. 101 = the node consumes a maximum of 1w of power from the cable. in addition, it consumes a maximum of 2w to enable the link and upper layers. 110 = the node consumes a maximum of 1w of power from the cable. in addition, it consumes a maximum of 5w to enable the link and upper layers. 111 = the node consumes a maximum of 1w of power from the cable. in addition, it consumes a maximum of 9w to enable the link and upper layers. m i p 2 p 1 p 0 p w r c d e l s p l o g i c a l i n v e r s e o f f i r s t q u a d l e t g a p _ c n t l 0 p h y _ i d 0 1
? 16 CXD1945R p0 to p2: port status field 11 = connected to the child node. 10 = connected to the parent node. 01 = not connected to another phy. 00 = this phy is not offered. indicates the port status. i: initiated_reset field indicates that this node issued the present bus reset. m: more_packets field this field is set to "1" when transmitting multiple self-id packets, but it is fixed to "0" for the CXD1945R.
? 17 CXD1945R [3] description of functions 3-1. link chip interface 3-1-1. connection method 3-1-1-1. dc connection d [ 0 : 3 ] s c l k l i n k p h y c x d 1 9 4 5 r l r e q c t l [ 0 : 1 ] l p s c m c / l i n k o n d i r e c t d v d d fig. 3-1. CXD1945R ?link chip connection diagram (dc connection)
? 18 CXD1945R 3-1-2. lps (link power status) the lps pin is the input signal for monitoring the power on/off status of the link connected to the CXD1945R. if the lps pin is continuously high for a period of 80ns or more, the CXD1945R recognizes that the link power is on, activates the phy-link interface and outputs sclk, d and ctl to the link. conversely, if the lps pin is continuously low for 2.56 s or more, the CXD1945R recognizes that the link power is off, deactivates the phy-link interface and stops sclk, d and ctl output to the link (hi-z). therefore, packet receive and status output to the link are not performed during this period, and information is not output after the phy-link interface is activated next. the CXD1945R operates as a repeater during this period. the l bit in the self-id packet is set to "0" during this period. in addition, if a link-on packet addressed to this node is received during this period, the link-on signal is output to the cmc/linkon pin. if lps is set high during link-on signal output, link-on signal output stops. the lps, sclk, d and ctl timing is shown in fig. 3-2. l p s s c l k t d i s t e n c t l / d fig. 3-2. lps timing table 3-1. lps timing constants symbol description min. max. unit time from when lps goes low until sclk, d and ctl go to hi-z time from when lps goes low until sclk, d and ctl become active 2.58 61 2.6 102 s ns tdis ten
? 19 CXD1945R 3-1-3. link interface (lreq, ctl[0:1], d[0:3]) the phy-link interface of the CXD1945R conforms to ieee std 1394-1995 annex j. the phy-link interface performs four operations: request using lreq, and status transmit, packet transfer and packet receive using ctl. operations using ctl (operations other than request) are first controlled by phy. when the CXD1945R receives a packet, it initiates packet receive operation on a priority basis. the ctl states and their meanings are given in tables 3-2 and 3-3. ctl[0:1] name description 00b 01b 10b 11b idle status receive grant idle status, with no operations. (default mode) the phy chip is transferring status information. the phy chip is transferring the received packet contents. the phy chip has granted the phy-link interface to the link chip in order to receive a packet. ctl[0:1] name description idle hold transmit reserved the link chip has completed transfer and released the interface. the link chip is holding the interface until the data is established for transfer. the link chip is requesting another packet transmission, without performing arbitration. the link chip is transferring the transmit packet data to the phy chip. reserved table 3-2. phy chip control mode 1 after the link has been granted control of the phy-link bus by grant above, operation switches to the modes shown in table 3-3. 00b 01b 10b 11b table 3-3. phy chip control mode 2 3-1-3-1. lreq the link chip inputs a serial signal synchronized to sclk to the lreq pin in order to access the phy register or to request packet transmit. this serial signal contains the request type, transfer packet speed, and read/write command information. the length of the lreq serial signal differs according to the request type; it is 7 bits for a bus request, 9 bits for a register read request, and 17 bits for a register write request. this serial signal must transmit a "0" at the end as the stop bit. l r n 1 l r n l r 0 l r 1 l r 2 l r 3 l r 4 l r n = l r e q n fig. 3-3. lreq stream
? 20 CXD1945R packet transfer requests are performed with a 7-bit length format as shown in table 3-4. bit name description 0 1 to 3 4 to 5 6 start bit request type request speed stop bit indicates the start of transfer. always transfer "1". indicates the request type shown in table 3-8. indicates the transfer speed of the phy chip. indicates the end of transfer. always transfer "0". bit name description 0 1 to 3 4 to 7 8 start bit request type address stop bit indicates the start of transfer. always transfer "1". indicates the request type shown in table 3-8. indicates the phy chip register address to be read. indicates the end of transfer. always transfer "0". lreq[4:5] data rate 00 01 100mbps 200mbps table 3-5. speed format phy chip register read requests are performed with a 9-bit length format as shown in table 3-6. register write requests are performed with a 17-bit length format as shown in table 3-7. bit name description 0 1 to 3 4 to 7 8 to 15 16 start bit request type address data stop indicates the start of transfer. always transfer "1". indicates the request type shown in table 3-8. indicates the phy chip register address to be written. indicates the phy chip register data to be written. indicates the end of transfer. always transfer "0". table 3-7. write register format table 3-4. request format table 3-6. read register format
? 21 CXD1945R lreq[1:3] name description 000 001 010 011 100 101 110, 111 immreq isoreq prireq fairreq rdreg wrreg reserved immediate request isochronous request priority request fair request read contents of set register write to set register reserved table 3-8. request type fair requests and priority requests must begin issuing lreq at least 1 sclk or more after ctl becomes idle. if ctl becomes receive either during or after the link issues these requests, the CXD1945R cancels the requests. therefore, the link must reissue these requests when ctl becomes idle next. the cycle master link issues prireq in order to transfer the cycle start packet. the link issues isoreq in order to transmit an isochronous packet. isoreq must be issued either during transmit or receive of the cycle start packet or an isochronous packet. the CXD1945R clears isoreq only when it wins at arbitration and transmits grant to the link, detects a subaction gap, or when a bus reset occurs. the link issues immreq during packet receive in order to transmit an ack packet. the link must confirm the destination_id of the received packet, and after confirming that the packet is addressed to this node, must issue immreq immediately in order to satisfy ack_response_time. the CXD1945R acquires the bus and returns grant to the link immediately after completing packet receive. if the link discovers a crc error, the link must not return any data to that grant. when a register write request is received, the CXD1945R immediately writes the data for that address. when a register read request is received, the CXD1945R outputs the data at that address to the link as a status transmission. if this output is interrupted by packet receive, the CXD1945R repeats the status output from the first bit until the status output is completed. when the CXD1945R receives a bus request (fairreq, prireq, isoreq, immreq), further bus requests are ignored until the received request is canceled by packet receive, packet transmit, subaction gap (only for isoreq, immreq), etc. if the CXD1945R receives the next register read request before the present register read request is completed, this operation is unstable. all bus requests are cleared by a bus reset.
? 22 CXD1945R 3-1-3-2. status output the CXD1945R outputs the information shown in table 3-9 to the link interface as the status output. the CXD1945R asserts "01b" to the ctl pin and outputs the information to the d[0:1] pins. the ctl pin outputs "01b" during the status output period. the CXD1945R normally outputs only the first 4 bits required by the link state machines as the status output. (arbitration reset gap, subaction gap, bus reset, phy interrupt) however, when a register read request is received from the link, all of the status information is output as the return value. also, when the CXD1945R finishes sending its own self-id packet during the self-id period (when the CXD1945R's physical_id is established), it automatically performs status output of the phy register information at address "00h" including its own physical_id to the link. if status output is interrupted by packet receive, etc., that status information is output repeatedly according to the following rules. information output before the interruption is cleared. if the information to be output was already output before the interruption, that status output is not repeated. status output is basically performed in 4-bit/16-bit units. 0 0 c t l [ 0 : 1 ] 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 d [ 0 : 1 ] s [ 0 , 1 ] s [ 2 , 3 ] s [ 4 , 5 ] s [ 6 , 7 ] s [ 1 4 , 1 5 ] 0 0 0 0 fig. 3-4. status bit name description 0 1 2 3 4 to 7 8 to 15 arbitration reset gap subaction gap bus reset phy interrupt address data arbitration reset gap detected subaction gap detected bus reset detected interrupt to host requested address of phy register returning the status status data table 3-9. status format the CXD1945R performs status output as a phy interrupt in the following case. when the bus configuration is detected as a loop
? 23 CXD1945R 3-1-3-3. transmit the CXD1945R performs arbitration when it receives a bus request from the link. if the CXD1945R wins at this arbitration, it returns grant (11b) and then idle to the ctl pin for 1 sclk cycle each as the grant to the link, and then grants ctl and d control to the link. after that, the link inputs transmit (10b) or hold (01b) to ctl and controls the phy-link interface. however, note that the CXD1945R allows the link to input idle (00b) for only 1 sclk first to prevent data collision on the ctl bus. (see fig. 3-5.) the link can input hold (01b) to hold the bus until the transfer data is ready, but this hold time cannot exceed the max_bus_hold time. c t l [ 0 : 1 ] p h y d r i v e l i n k d r i v e 1 0 0 m b p s 2 0 0 m b p s 0 0 1 1 0 0 z z z z z z z z z z z z z z z z 0 0 d [ 0 : 3 ] 0 0 0 0 0 0 z z z z z z z z z z z z z z z z 0 0 c t l [ 0 : 1 ] z z z z z z 0 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 z z d 0 z z z 0 d 0 0 d 2 d 4 d 2 n 0 0 z d 1 z z z 0 d 1 0 d 3 d 5 d 2 n + 1 0 0 z d 0 z z z 0 d 0 0 d 4 d 8 d 4 n 0 0 z d 1 z z z 0 d 1 0 d 5 d 9 d 4 n + 1 0 0 z d 2 z z z 0 d 2 0 d 6 d 1 0 d 4 n + 2 0 0 z d 3 z z z 0 d 3 0 d 7 d 1 1 d 4 n + 3 0 0 z z z z z 0 0 0 0 0 0 0 0 fig. 3-5. transmit
? 24 CXD1945R after the last bit of the packet data has been input, the link inputs idle (00b) or hold (01b) for 1sclk cycle and then inputs idle for 1sclk cycle. after that, the CXD1945R controls the phy-link interface. the hold (01b) bit is used to transfer the next packet without releasing the serial bus after the link completes packet transfer. when the CXD1945R detects the hold bit, it waits for the min_packet_separation time and then outputs transmit to the ctl pin again for the link. the link then performs packet transfer operation in the same manner as above. this hold operation is used when transferring a response packet after ack packet transmit, and when transferring multiple isochronous packets during the same isochronous cycle. (subaction concatenation) however, note that in this case the CXD1945R recognizes that the packet speed for the second and subsequent packets is the same as the initial packet speed.
? 25 CXD1945R 3-1-3-4. receive when the CXD1945R receives a packet, it outputs receive (10b) to the ctl pin and "1" to the d pin for the link. after that the CXD1945R outputs the speed code (sp) and commences packet data output. the CXD1945R continues asserting receive (10b) to the ctl pin until data receive is completed. after the CXD1945R asserts receive, the receive operation may complete without outputting the packet data. if the link supports only 100mbps, the speed code (sp) must be checked and 200mbps receive packet data ignored. 0 0 c t l [ 0 : 1 ] p h y d r i v e 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 d 1 1 1 1 1 s p 1 d 1 d 3 d 2 n + 1 0 0 0 0 d 0 2 0 0 m b p s 1 1 1 1 s p 0 d 0 d 4 d 4 n 0 0 0 0 d 1 1 1 1 1 s p 1 d 1 d 5 d 4 n + 1 0 0 0 0 d 2 1 1 1 1 s p 2 d 2 d 6 d 4 n + 2 0 0 0 0 d 3 1 1 1 1 s p 3 d 3 d 7 d 4 n + 3 0 0 0 0 d 0 1 0 0 m b p s 1 1 1 1 s p 0 d 0 d 2 d 2 n 0 0 0 fig. 3-6. receive sp[0:3] data rate 00xx 0100 100mbps 200mbps table 3-10. speed code (sp[0:3])
? 26 CXD1945R 3-1-4. cmc/linkon pin connection this pin is normally used as the cmc (configuration manager capable) input pin. the value input here is reflected to the c (contender) field in the self-id packet. when cmc is high, this indicates that this node has bus manager functions. this pin also functions as the link-on signal output pin. therefore, it must be pulled up or down to dv dd or dv ss by a 10k resistor as shown in figs. 3-7 and 3-8. the link-on signal is an ac signal with a frequency of 6.144mhz and a duty of 50%, and is output when a link-on packet addressed to this node is received while lps is low and the CXD1945R recognizes the link power as being off. output of this signal starts after the link-on packet is received and continues until either lps goes high and the CXD1945R recognizes the link power as being on or a bus reset occurs. the cmc/linkon connection when cmc = 1 is shown in fig. 3-7, and when cmc = 0, in fig. 3-8. 7 8 1 0 k d v d d c x d 1 9 4 5 r l i n k - o n fig. 3-7. cmc/linkon pin when cmc = 1 7 8 1 0 k d v s s c x d 1 9 4 5 r l i n k - o n fig. 3-8. cmc/linkon pin when cmc = 0 3-1-5. direct this pin inputs the phy-link interface connection information. if the phy-link interface is dc connected, this pin is set high. the CXD1945R does not support ac connection.
? 27 CXD1945R 3-2. cable interface 3-2-1. cable interface circuit fig. 3-9 shows the cable interface connection circuit. 1 . 8 5 v 0 . 8 v 1 0 k w c u r r e n t d r i v e r d i f f e r e n t i a l p a c k e t r e c e i v e r c o m p a r a t o r ( z / 0 ) c o m p a r a t o r ( z / 1 ) c o m m o n m o d e c o m p a r a t o r c u r r e n t d r i v e r d i f f e r e n t i a l p a c k e t r e c e i v e r c o m p a r a t o r ( z / 0 ) c o m p a r a t o r ( z / 1 ) c o m m o n m o d e c o m p a r a t o r 1 0 k w 1 0 k w 1 0 k w 5 5 w 5 5 w ( 3 w , 1 / 1 0 w ) 5 k w ( 5 % , 1 / 1 0 w ) 2 7 0 p f 0 . 3 3 f t p b i a s 5 5 w 5 5 w t p a t p a # t p b t p b # 1 . 8 5 v 0 . 8 v 1 0 k w c u r r e n t d r i v e r d i f f e r e n t i a l p a c k e t r e c e i v e r c o m p a r a t o r ( z / 0 ) c o m p a r a t o r ( z / 1 ) c o m m o n m o d e c o m p a r a t o r c u r r e n t d r i v e r d i f f e r e n t i a l p a c k e t r e c e i v e r c o m p a r a t o r ( z / 0 ) c o m p a r a t o r ( z / 1 ) c o m m o n m o d e c o m p a r a t o r 1 0 k w 1 0 k w 1 0 k w 5 5 w 5 k w 2 7 0 p f 0 . 3 3 f t p b i a s 5 5 w 5 5 w 5 5 w t p a t p a # t p b t p b # fig. 3-9. cable interface
? 28 CXD1945R dedicated ieee 1394 cables are used as the cable media, and two sets of shielded twisted pair cables are used for data transmit and receive. as shown in fig. 3-9, each twisted pair cable connects the tpa pair of this node with the tpb pair of the opposing node. both the tpa and tpb sides require two 55 ( 3 , 1/10w) terminating resistors in accordance with the cable impedance. locate these terminating resistors as close to the ic pins as possible. tpbias (typ. 1.85v) is connected to the node between the terminating resistors on the tpa side in order to set the cable in-phase dc potential. connect 0.33 f to tpbias for decoupling. the in-phase current for the speed signal described hereafter is supplied from this capacitor. note that this capacitor is used to compensate the phase of the internal operational amplifier, so it is necessary even when not actually using tpbias (unused port, etc.). connect 5k ( 5%, 1/10w) and 270pf (10v) to the node between the terminating resistors on the tpb side to pull it down. as a result, when the cable is disconnected and the dc bias from the opposing node tpa is cut off, the tpb side dc potential drops to near 0v and this can be detected by an in-phase comparator. the 270pf is for decoupling. fig. 3-9 shows the case in which the coil located between the terminating resistor and the cable is a common mode coil (250nh, k > 0.97) for limiting the in-phase signal bandwidth. when using a coil, connect it in this position to reduce electromagnetic interference (emi) due to in-phase noise generated at the signal transition point. this has no effect on data transmit or receive, so there are no problems with communication even if a coil is not used. 3-2-2. description of cable interface operation the communication phases with the opposing node can be broadly divided into "arbitration" and "data packet transmit/receive". arbitration transmit/receive is ternary logic (0, 1, z; differential) and is performed by full- duplex communication with the speed signal (in-phase) superimposed. packet transmit/receive is binary logic (0, 1; differential) and is performed by semi-duplex communication. in either case, transmit is performed by the high impedance current driver, and receive by detecting the differential or in-phase voltage at both ends of the terminating resistors with a comparator or a packet receiver. the signals transmitted and received by tpa and tpb are as follows. tpa: differential signal: arbitration transmit/receive, packet transmit (strobe signal), packet receive (data signal) in-phase signal: speed signal receive, cable bias (tpbias) tpb: differential signal: arbitration transmit/receive, packet transmit (data signal), packet receive (strobe signal) in-phase signal: speed signal transmit, connection status detection fig. 3-10 shows the current driver status, cable current, and the differential and in-phase voltage waveforms observed at the terminating resistors during various data transmit. (fig. 3-10 illustrates various signal states, and does not indicate the waveform for a particular bus phase.)
? 29 CXD1945R 4 m a 2 m a s e n d p a c k e t " 0 " o r a r b i t r a t i o n " 0 " 5 5 5 5 2 m a 2 2 0 m v 5 5 5 5 4 m a 4 m a 8 m a 4 m a 0 . 5 m a 2 m a s e n d a r b i t r a t i o n " 0 " & s p e e d s i g n a l 5 5 5 5 7 m a 2 2 0 m v ( d i f f ) 5 5 5 5 0 . 5 m a 0 . 5 m a 8 m a 7 . 5 m a 1 9 2 . 5 m v ( c o m m o n ) 7 . 5 m a 2 m a s e n d a r b i t r a t i o n " 1 " & s p e e d s i g n a l 5 5 5 5 7 m a 2 2 0 m v ( d i f f ) 5 5 5 5 0 . 5 m a 0 . 5 m a 8 m a 0 . 5 m a 1 9 2 . 5 m v ( c o m m o n ) 3 . 5 m a s e n d a r b i t r a t i o n " z " & s p e e d s i g n a l 5 5 5 5 7 m a 0 m v ( d i f f ) 5 5 5 5 4 . 5 m a 4 . 5 m a 8 m a 8 m a 3 . 5 m a 1 9 2 . 5 m v ( c o m m o n ) 4 m a 2 m a s e n d p a c k e t " 1 " o r a r b i t r a t i o n " 1 " 5 5 5 5 2 m a 2 2 0 m v 5 5 5 5 4 m a 4 m a 8 m a 4 m a s e n d a r b i t r a t i o n " z " 5 5 5 5 0 m v 5 5 5 5 fig. 3-10. driver current and output waveforms t p # t p + 2 2 0 m v 2 2 0 m v t p d i f f e r e n t i a l 1 . 8 5 v 1 9 2 . 5 m v t p c o m m o n "z" "0" arbitration spd sig "off" spd sig "on" spd sig "off" "1" arbitration "z" arbitration spd sig "off" spd sig "on" spd sig "off" spd sig "off" spd sig "on" spd sig "off"
? 30 CXD1945R 3-2-3. cps (cable power status) the cps pin is connected to the cable power (vp) via an external resistor rcps (normally 226k ), and detects when the cable power drops below the threshold (normally 7.5v). when not used, connect to av dd . the relationship between the threshold value vt and the external resistor rcps is given by the following formula. vt = 1.85 + rcps 25e-6 3-2-4. processing for unused ports the CXD1945R has three ports. when using only one or two of these ports, connect the unused port pins as follows. unused port pin symbol connection tpap, tpan tpbp, tpbn tpbias no connected av ss to av ss via 0.33 f the circuit diagram when using only one port is shown below as an example. 6 0 5 9 5 5 w ( 3 w , 1 / 1 0 w ) 5 k w ( 5 % , 1 / 1 0 w ) t o / f r o m c a b l e 5 5 w 0 . 0 1 f t p a 0 p c x d 1 9 4 5 r t p a 0 n 5 5 w 5 5 w 2 7 0 p f t p b 0 p t p b 0 n t p a 1 p t p a 1 n t p b 1 p t p b 1 n t p a 2 p t p a 2 n t p b 2 p t p b 2 n t p b i a s 0 t p b i a s 1 t p b i a s 2 0 . 3 3 f 0 . 3 3 f 0 . 3 3 f a v s s 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 fig. 3-11. circuit diagram when using only one port table 3-11. processing for unused port pins
? 31 CXD1945R 3-3. clock circuit 3-3-1. crystal oscillator an oscillator output frequency of 24.576mhz 100ppm is necessary. the crystal itself should have an accuracy of 50ppm when load capacitance of 10pf is connected. 3-3-2. pll the pll multiplies the 24.576mhz output from the crystal oscillator by 8 times to generate 196.608mhz. pll lock time is 100 s or less. 3-4. hardware reset a reset pulse with a minimum width of 15ms is generated during power-on by connecting the purb pin to ground via a 0.1 f external capacitor. all state machines are reset by externally applying low level to this pin.
? 32 CXD1945R application circuit 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 p c 1 p c 2 d v s s d v s s l p s l r e q d v d d s c l k d v s s c t l 0 c t l 1 d v d d d 0 d 1 d v s s d 2 d 3 d v d d d v s s d v s s a v s s v c o r l f a v d d 1 a v s s a v s s a v s s x i x o a v d d 1 a v s s a v d d 1 p u r b d v s s d v d d d v d d d v s s d v s s d v s s d v s s n c n c d v d d n c n c d v s s d v s s d v s s d v s s d v s s d v s s a v s s a v d d 2 d v s s t e s t 1 t e s t 0 d i r e c t c m c / l i n k o n p c 0 d v d d t p a 0 p t p a 0 n t p b 0 p t p b 0 n t p a 1 p t p a 1 n c a b l e i / f t p b i a s t p b 1 p t p b 1 n t p a 2 p t p a 2 n t p b 2 p t p b 2 n t p b i a s 0 t p b i a s 1 t p b i a s 2 a v d d 1 a v s s c p s r e x t v r e f 1 3 0 p f 1 0 p f 1 0 p f 2 4 p f 0 . 1 f 0 . 1 f 0 . 0 1 f a g n d ( v r e f ) 2 2 0 k w g u a r d 0 . 1 f 0 . 1 f 0 . 1 f 1 . 2 k w 1 . 8 8 k w 0 . 1 f 0 . 1 f a v s s 3 3 f 0 . 1 f 1 1 k w ( 0 . 2 % ) v p ( c a b l e s u p p l y v o l t a g e ) 6 2 0 w ( 0 . 2 % ) 1 8 k w ( 0 . 2 % ) 5 1 0 w ( 0 . 2 % ) a v s s v p o w e r ( 3 . 3 v ) 3 3 f 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f d v s s 3 3 f 0 . 1 f 0 . 1 f 0 . 1 f 2 2 f 0 . 1 f l o o p f i l t e r 1 . 2 0 k w ( 5 % ) 1 . 8 8 k w ( 5 % ) 1 2 5 p f ( 5 % ) 2 4 p f ( 5 % ) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 33 CXD1945R cable interface connection circuit example 6 0 5 9 5 6 w 5 % , 1 / 1 0 w 5 . 1 k w 5 % , 1 / 1 0 w t o / f r o m c a b l e 5 6 w 0 . 0 1 f t p a 0 p c x d 1 9 4 5 r t p a 0 n 5 6 w 0 . 0 1 f 5 6 w 5 6 w 5 6 w 2 7 0 p f , 1 0 v t p b 0 p t p b 0 n t p a 1 p t p a 1 n t p b 1 p t p b 1 n t p a 2 p t p a 2 n t p b i a s 0 t p b i a s 1 t p b i a s 2 0 . 3 3 f , 1 0 v 0 . 3 3 f 0 . 3 3 f 4 7 0 0 p f , 1 k v a v s s 1 0 . 1 m w 1 0 . 1 m w f r a m e s h i e l d v g s h i e l d 5 8 5 7 5 6 5 5 4 8 4 7 4 6 5 . 1 k w 5 6 w 0 . 0 1 f 5 6 w 5 6 w 5 6 w 2 7 0 p f 5 . 1 k w 5 6 w 5 6 w 2 7 0 p f 5 4 5 3 5 2 5 1 t p b 2 p t p b 2 n 5 0 4 9 reduce the parasitic impedance of the cable interfaces (tpa, tpb) as much as possible. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 34 CXD1945R package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 a l l o y p a c k a g e s t r u c t u r e 0 . 2 m 8 0 p i n l q f p ( p l a s t i c ) 0 . 5 g l q f p - 8 0 p - l 2 3 1 1 2 0 2 1 4 0 6 0 4 1 8 0 6 1 1 2 . 0 0 . 1 1 4 . 0 0 . 2 0 . 5 0 . 2 0 . 0 5 0 . 1 0 . 1 7 0 . 0 5 1 . 4 m i n 1 . 7 m a x 0 1 0 0 . 1 0 . 0 5 0 . 5 0 . 1 a d e t a i l a

▲Up To Search▲

Price & Availability of CXD1945R

	To Download CXD1945R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .